Robert J Strain

June 12, 2022

EDUCATION
	BSEE (High Honors), University of Illinois, Urbana, 1958
	MSEE, University of Illinois, 1959
	Ph. D., University of Illinois, 1963 (EE and Microwave Physics)
EXPERIENCE
	R Strain Consulting (July 1999 to date)
		During period from July 1999 through June 2000, I worked half time as a contract employee of National Semiconductor, continuing to promote foundry relationships and solve technical problems. (complete)
		Since April, 2000, I have undertaken consulting projects in the following areas:
		Advising fabless company about foundry business terms and conditions (complete)
		Working with Nif/T New Business Architects as technical expert on selected projects:
			Acquisition of FLASH start-up by established IC company (complete)
			Venture funding of RF start-up (complete)
			Corporate funding and licensing of (different) FLASH start-up (complete)
			Investigating potential of optical communications and thermal component start-up companies (complete)
			Assisting with the effort to arrange the acquisition of an RF design company.
			Providing technical assistance to start-up dedicated to mitigating leakage problems with 90 nm and finer CMOS, and continuing through two subsequent generations of related technology.  (ongoing)
			Investigating potential of solid battery start-up company and assisting their creation of intellectual property.  (ongoing)
			Assisting technology acquirer by analyzing technical validity and patent coverage of an alternative memory cell. (complete)
			Assisting company involved in smart electric power transmission with creation of intellectual property/  (ongoing)
		Advising second tier silicon IC foundry about customer support and technology options (complete)
		Defining and designing gigahertz components for packaging company (complete)
		Advising start-up in nano-ionic non-volatile memory technology concerning yield and qualification. (complete)
		Supplying technical analysis to major IC company regarding patents (complete)
		Starting in December, 2003, advised San Francisco law firm on patents and trade secrets in their successful representation of a major Taiwan foundry against a major PRC foundry. (completed in 2009)
		Starting in August, 2008, advised international law firm (Washington office) in their successful defense of a major US semiconductor firm against patents asserted by another US semiconductor firm. (completed in 2009)

		Starting in February, 2011, advised San Francisco law firm on patents asserted against a major Taiwan foundry by a small packaging technology firm. (in abeyance in 2014, settled in 2017)
		Starting in April, 2013, advised San Francisco law firm on patents asserted against a major Taiwan foundry by a European semiconductor firm. (discontinued in 2013)
		Starting in October, 2013, advised San Francisco law firm on patents asserted against a major Taiwan foundry by a US design technology firm. (discontinued in 2014)
		Starting in April, 2014, advised San Francisco law firm representing major US non-volatile memory company in their action against Korean firm that utilized stolen trade secret information.  (discontinued in 2015)
		Starting in March, 2015, advised San Francisco law firm on patents asserted against a major Taiwan foundry by a non-practicing entity. (discontinued in 2015)
	National Semiconductor Corporation, Santa Clara, CA
		Director, Foundry Technology Management (August, 1996 - July 1999)
		I directed efforts to both expand and rationalize National’s Foundry relations, including new agreements with TSMC and IBM. A major focus was creating the support necessary for effective design and product engineering in cooperation with external foundries. I also managed the transfer of several technologies from National to outside foundries.
		Deputy Director, National Semiconductor Research Laboratory (June, 1995 - Aug. 1996)
		I helped create an NSC technology strategy, based on a ten-year future outlook created through research and customer contacts. As Chairman of the Process Development Council, I helped rationalize and sustain NSC’s Wafer Process Roadmaps and the NSC road mapping process.
		Strategic Technology Director (January 1988 - June 1995)
		I joined NSC through the Fairchild acquisition, taking the title Strategic Technology Director, a title that has encompassed a wide variety of assignments. These assignments have included: DRAM alliance negotiator and analyst, temporary (11 month) Product Line Director for High Performance Memories, Total Quality Manager, process transfer project manager, and acting director of Process Development. During these assignments, I created several technology business processes that help bind the company together. I moved bipolar processes between manufacturing sites, and worked on alliances with WSI, IBM, Mitsubishi and Matsushita. On two occasions, I filled a critical management gap, head of Wafer Process Development, for an extended period. During the High Performance Memory assignment, I managed our ramp from no shipments to about $2.5 million per month.
	Fairchild Semiconductor Corporation, Cupertino, CA
		Manager, Business Development (January, 1986 - December, 1987)
		In this role, I set up strategic alliances with Brooktree and AT&T and second source agreements with Hitachi and Motorola. During the period when a Fujitsu acquisition seemed possible, I was the coordinator for all technical dialog between Fairchild and Fujitsu.
		Project Manager, Nagasaki Wafer Fab (January, 1985 - December, 1985)
		I guided the planning and justification of a major state-of-the-art IC manufacturing facility. I recruited the key managers for that plant, which made good wafers before being sold to Sony by Schlumberger.
		Manager, Device Technology, Fairchild Research Center (March 1982 - January 1985)
		My department carried out the exploratory development in support of the 1-micron generation of IC's.
		Manager of Engineering, MOS Division (February 1980 - March 1982)
		My responsibilities in South San Jose were the development of new IC products and processes for the MOS Division, managing resources ranging from CAD to a pilot line.
	Harris Semiconductor, Melbourne, FL
		Director of Corporate Liaison (October 1978 - February 1980)
		Senior Scientist (February 1976 - October 1978)
		Under both these titles, I was a technical consultant throughout Harris Corporation on the utilization of integrated circuits. I defined and introduced selected circuits sold by Harris.
		MOS Memory Manager (January 1975 - February 1976)
		Memory Development Manager (June 1973 - January 1975)
		My departments initiated two of Harris's important product lines for the late 70's, "Generic" PROM's and CMOS memories.
	Bell Telephone Laboratories, Murray Hill, NJ
		Supervisor, Interface Studies (June 1968 - June 1973)
		Our work included device physics studies of MOS and trap-controlled structures and product definition and development of CCD's for memory and signal processing.
		Member of Technical Staff (May 1965 - June 1968)
		I was an individual contributor in the development and application of GaP light emitting diodes.
	Standard Telecommunication Laboratories, Harlow, Essex, England
		Research Engineer (September 1963 - May 1965)
		Far infrared studies and GaAs photoconductivity.
	Other Experience
		University teaching and research, TV broadcast engineering, power supply engineering.
PATENTS AND PUBLICATIONS
	A list of 24 publications is available on request.  A list of 35 issued patents is available on request.
PROFESSIONAL ACTIVITIES
	Chairman of Gordon Research Conference on MOS Interfaces (1973)
	Co-Chairman of International Symposium on Semiconductor Manufacturing (1995)
	U.S./European Program Chair of ISSM (1996)